Various electronic devices digitalized in recent years with the progress in semiconductor technology that executes the digital signal processing of microprocessors, memory IC, etc. However, the physical quantity of the natural world is an analog quantity, and it is necessary to convert analog signals into digital signals. Therefore conventionally, an A/D convertor was widely used.
Generally, there are various modes of A/D convertors such as the successive comparison type, integration type, oversampling type, etc., but the successive comparison type of A/D convertor is used in the general-purpose products due to the favorable balance between the precision, speed, and cost.
When a successive comparison type of A/D converter in the conventional technology is explained, there are a comparator, a successive comparison register, a control circuit, and a D/A conversion circuit. The D/A conversion circuit forms a comparison voltage DA from the reference voltage V.sub.ref by referring to the value of the successive comparison register, and is connected so as to output to the comparator, with the comparator comparing the input voltage A.sub.in, which is the conversion target, with the input comparison voltage DA and is composed to output the comparison result to the successive comparison register as shown in the block diagram in FIG. 12.
The value of the successive comparison register is changed according to the input comparison result of the comparator, the D/A conversion circuit sets the comparison voltage DA according to the value of the successive comparison register after the change, and is composed for the comparator to execute a comparison between the input voltage A.sub.in and the comparison voltage DA that was set. When this type of comparison of the comparator and setting of the D/A conversion circuit are repeatedly executed, conversion of the input voltage A.sub.in into digital voltage data with the necessary precision becomes possible.
A method for converting the input voltage A.sub.in into digital voltage data of M bits with one comparator using an A/D comparator with the aforementioned constitution will be explained.
First of all, the control circuit starts the operation with the START signal and the following processes are executed.
(1) The successive register is initialized (hereafter "successive comparison register" will be referred to as "register").
(2) "1" is stored in the uppermost order bit B.sub.m of the register.
(3) One comparison voltage DA is set based on the value of the register. The value of the register at this time is "1" in only the uppermost order bit B.sub.m, so the comparison voltage DA is set to 1/2 V.sub.ref.
(4) The input voltage A.sub.in and comparison voltage DA are compared and the comparison result is obtained.
(5) If the comparison result is 1, namely, if input voltage A.sub.in is more than comparison voltage DA, uppermost order bit B.sub.m of the register value is left as 1. If the comparison result is 0, namely, if input voltage A.sub.in is less than comparison voltage DA, uppermost order bit B.sub.m of the register value is made 0.
(6) "1" is stored in second bit B.sub.m-1, of the register. As a result, the value of the register becomes "1100 . . . 0" or "0100 . . . 0."
(7) Second comparison voltage DA is set based on the content of said register.
If the value of the register is "1100 . . . 0," comparison voltage DA is set to 3/4 V.sub.ref ; if it is "0100 . . . 0," comparison voltage DA is set to 1/4 V.sub.ref.
(8) The comparison result is obtained by comparing input voltage A.sub.in with comparison voltage DA that was set.
(9) Second bit B.sub.m-1, is decided according to the process in 5 above based on the comparison result.
(10) "1" is stored in third bit B.sub.m-2 of the register and the same processes as those subsequent to 7 are repeatedly executed.
By repeating said processes, the value of the register that indicates the digital voltage data of input voltage A.sub.in becomes high in precision by 1 bit each. When the processing of last bit B.sub.1 is completed and the register value of the M bits is decided, the control circuit outputs an END signal, the value of the register thereof is extracted as digital voltage data of M bit precision, and the A/D conversion process ends.
Therefore, it is possible to obtain digital voltage data of high precision in the successive comparison type of A/D converter even if the number of comparators and comparison voltage setting circuits is minimal.
Incidentally, it is necessary to repeatedly execute the comparison operation for the precision level of the digital voltage data in a successive comparison type of A/D converter. In the aforementioned example, M times of comparison operations are necessary since digital voltage data of M bits are obtained with one comparison.
In this case, the setting frequency of comparison voltage DA is also M times but comparison voltage DA is set based on the comparison result, so if the comparison result errs even once, all the comparison voltages set thereafter become erroneous. Therefore, the digital voltage data in case there is a comparison miss become that which does not correctly express the value of the input voltage.
In this type of comparison miss, there are those originating in erroneous operation of the comparator or an erroneous voltage contained in comparison voltage DA, but in addition to these, there are cases of originating in the voltage value of input voltage A.sub.in fluctuating during the time that the comparison operation is being executed repeatedly.
Input voltage A.sub.in is normally fed from the sample-hold circuit provided in front of the A/D converter, but it is known that oscillation as in the graph indicated with code (A'.sub.in) in FIG. 13 is observed depending on the operational state of said sample-hold circuit.
Therefore, in the conventional technology, the A/D converter is made to wait until time (T.sub.0), at which time the oscillation attenuates sufficiently after sample hold of input voltage A.sub.in is executed and the comparison operation is started after input voltage A.sub.in stabilizes.
However, a parasitic capacity exists within the comparator so two input terminals of the comparator are connected by said parasitic capacity. Comparison voltage DA input to one input terminal in this type of comparator is changed in voltage value each time a comparison operation is executed, so when said change in comparison voltage DA influences the other input terminals, the setting of comparison voltage DA is influenced even after the oscillation has been sufficiently attenuated, input voltage A.sub.in connected to the other input terminal fluctuates, and a comparison miss may be generated.
Incidentally, the voltage value of comparison voltage DA fluctuates greatly immediately after the start of the comparison operation (e.g., the amount of change in the comparison voltage between the first time and the second time is a size of 1/4 V.sub.ref), so the amount of fluctuation immediately after the start of the comparison operation becomes large even in input voltage A.sub.in , which is influenced by it. As was noted above, even after the vibration of input voltage A.sub.in has been attenuated, there is a tendency for a comparison miss to be generated immediately after starting the comparison operation.
Therefore, a countermeasure was taken even in the conventional technology. When setting comparison voltage DA, the upper limit voltage which added and a lower limit voltage that which subtracted a prescribed voltage value to said comparison voltage DA are set; after the comparison result of input voltage A.sub.in and comparison voltage DA is obtained, input voltage A.sub.in is successively compared with the upper limit voltage and the lower limit voltage, and whether there is an inconsistency between the comparison results of the voltages was checked.
However, the change in comparison voltage DA becomes less each time setting is executed and the change in comparison voltage DA is minimal near the end of the M times of comparison operations (e.g., the amount of change in the comparison voltage between the 9th time and the 10th time is 1/1024 V.sub.ref).
Therefore, when the upper limit voltage and the lower limit voltage are set to be able to accommodate the great fluctuation in initial input voltage A.sub.in at the start of the comparison operation, a comparison miss according to the trace fluctuation in comparison voltage DA cannot be detected since the oscillation of input voltage A.sub.in also gradually becomes less, a trace error included in the obtained digital voltage data is created, and a problem is generated.
Also, in this type of conventional technology, the conversion time becomes long due to requiring an excessive waiting time, redoing the comparison when a comparison miss is detected, etc., so it is unsuitable for the A/D converters of the recent years that require high speed operation.
The present invention was made to solve said inconveniences in the conventional technology, and the objective is to provide a technology capable of accurately converting input voltage A.sub.in into digital voltage data.
Also, the objective is to provide a technology that can obtain a correct digital voltage data in a short conversion time.